1. Technical Field
This invention relates in general to electronic circuits and, more particularly, to digital phase lock loop circuits.
2. Description of the Related Art
In order to produce high frequency clocks, as required by many of today's VLSI (Very Large Scale Integration) circuits, integrated clock multipliers are used. Frequency multiplication can be produced by a number of different circuits. The most common of these circuits is the analog phase lock loop circuit (PLL).
The PLL suffers from many shortcomings. First, it cannot be digitally simulated, so verification of lock-up and jitter specifications is difficult. Secondly, PLLs require external components, which are not desirable in many applications.
Digital PLLs (DPLLs), on the other hand can be readily simulated and do not require external components. They offer other advantages, such as faster time-to-lock and they can maintain a lock output frequency even after loss of the reference signal. Once the reference signal is regained, a DPLL can remain in lock, unless there has been significant drift during loss of the signal.
Heretofore, however, many DPLL designs have had their own shortcomings. First, they may have excessive power requirements for many applications. Second, they may be unable to meet jitter requirements in some cases.
Therefore, a need has arisen for a low power DPLL able to meet strict jitter requirements.